URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 614

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Rev	Log message	Author	Age	Path
614	Changed to support new debug if.	simons	8331d 00h	/
613	init: trap exception occurs always; initialization of sr not needed anymore	markom	8331d 21h	/
612	Tick timer period extended to meet real timing.	simons	8331d 22h	/
611	EEAR register is not changed by trap, sys, int, tick and range exception.	simons	8333d 00h	/
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8333d 00h	/
609	Added wb_err_o to flash and sram i/f for testing the buserr exception.	lampret	8333d 00h	/
608	Range exception removed from test.	simons	8333d 19h	/
607	single step steps just one instruction ^c bug fixed	markom	8333d 20h	/
606	raw register range bug fixed; acv_uart test passes	markom	8334d 20h	/
605	simulator prints out a message, when gdb is not attached and stall occurs; OV flag fixed	markom	8334d 20h	/
604	mul test repaired - signed multiplication; obsolete pic test removed; make check pass	markom	8334d 20h	/
603	fixed bfd	markom	8334d 22h	/
602	Renamed targets. Switched off debug.	lampret	8335d 21h	/
601	or1k has anly one external interrupt exception. Tick timer exception added.	simons	8336d 08h	/
600	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8336d 09h	/
599	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8336d 09h	/
598	Fixed SR[EXR] (this is now actually SR[TEE])	lampret	8336d 18h	/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8336d 18h	/
596	SR[TEE] should be zero after reset.	lampret	8336d 22h	/
595	Fixed 'the NPC single-step fix'.	lampret	8337d 18h	/

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Subversion Repositories or1k_old

[/] - Rev 614

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