URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 631

Rev	Log message	Author	Age	Path
631	Real cache access is simulated now.	simons	8326d 14h	/
630	some bug fixes in store buffer analysis	markom	8326d 23h	/
629	typo fixed	markom	8327d 03h	/
628	This commit was manufactured by cvs2svn to create tag 'pre-GNU-merge'.		8327d 03h	/
627	or32 restored	markom	8327d 03h	/
626	store buffer added	markom	8327d 03h	/
625	Bus error bug fixed. Cache routines added.	simons	8327d 20h	/
624	Added logging of writes/read to/from SPR registers.	ivang	8327d 20h	/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8327d 22h	/
622	Cache test works on hardware.	simons	8328d 01h	/
621	Cache test works on hardware.	simons	8328d 02h	/
620	use ARITH_SET_FLAG to turn off set flag by arith. instructions	markom	8328d 02h	/
619	all test pass, after newest changes	markom	8328d 02h	/
618	Fixed display of new 'void' nop insns.	lampret	8328d 11h	/
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8328d 11h	/
616	flags test added	markom	8330d 21h	/
615	cmov and extxx instructions; add, addi, and, andi now set flag	markom	8330d 21h	/
614	Changed to support new debug if.	simons	8331d 05h	/
613	init: trap exception occurs always; initialization of sr not needed anymore	markom	8332d 02h	/
612	Tick timer period extended to meet real timing.	simons	8332d 03h	/