URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 807

Rev	Log message	Author	Age	Path
807	sched files moved to support dir	markom	8222d 03h	/
806	uart now partially uses scheduler	markom	8222d 03h	/
805	kbd, fb, vga devices now uses scheduler	markom	8222d 03h	/
804	memory regions can now overlap with MC -- not according to MC spec	markom	8222d 21h	/
803	Free irq handler fixed.	simons	8225d 14h	/
802	Cache and tick timer tests fixed.	simons	8227d 01h	/
801	l.muli instruction added	markom	8228d 21h	/
800	Bug fixed.	simons	8229d 19h	/
799	Wrapping around 512k boundary to simulate real hw.	simons	8233d 12h	/
798	Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary.	simons	8233d 12h	/
797	Changed hardcoded address for fake MC to use a define.	lampret	8233d 14h	/
796	Removed unused ports wb_clki and wb_rst_i	lampret	8233d 14h	/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8233d 18h	/
794	Added again just recently removed full_case directive	lampret	8233d 18h	/
793	Added synthesis off/on for timescale.v included file.	lampret	8233d 18h	/
792	Fixed port names that changed.	lampret	8233d 18h	/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8233d 18h	/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8233d 18h	/
789	Added response from memory controller (addr 0x60000000)	lampret	8233d 19h	/
788	Some of the warnings fixed.	lampret	8233d 19h	/