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Rev Log message Author Age Path
991 Different memory controller. simons 8014d 07h /
990 Test is now complete. simons 8014d 07h /
989 c++ is making problems so, for now, it is excluded. simons 8015d 15h /
988 ORP architecture supported. simons 8016d 06h /
987 ORP architecture supported. simons 8016d 14h /
986 outputs out of function are not registered anymore markom 8016d 14h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8017d 02h /
984 Disable SB until it is tested lampret 8017d 02h /
983 First checkin lampret 8017d 04h /
982 Moved to sim/bin lampret 8017d 04h /
981 First checkin. lampret 8017d 04h /
980 Removed sim.tcl that shouldn't be here. lampret 8017d 04h /
979 Removed old test case binaries. lampret 8017d 04h /
978 Added variable delay for SRAM. lampret 8017d 04h /
977 Added store buffer. lampret 8017d 04h /
976 Added store buffer lampret 8017d 04h /
975 First checkin lampret 8017d 04h /
974 Enabled what works on or1ksim and disabled other tests. lampret 8017d 06h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8019d 10h /
972 Interrupt suorces fixed. simons 8019d 11h /

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