URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 105

Rev	Log message	Author	Age	Path
105	Wrong pci_bridge32.v file included in the project!	mihad	7616d 15h	/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7616d 18h	/
103	Added test application and modified files to support it.	mihad	7663d 15h	/
102	Cleanup!	mihad	7663d 15h	/
101	Added simulation files.	mihad	7663d 15h	/
100	Cleanup!	mihad	7663d 15h	/
99	Cleanup!	mihad	7663d 16h	/
98	Cleanup.	mihad	7663d 16h	/
97	Doing a little bit of cleanup.	mihad	7663d 16h	/
96	Update!	mihad	7663d 16h	/
95	Removed this file, because it was too large - long download time.	mihad	7663d 16h	/
94	Changed one critical PCI bus signal logic.	mihad	7663d 16h	/
93	Added a test application!	mihad	7663d 23h	/
92	Update!	mihad	7664d 00h	/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7699d 13h	/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7699d 13h	/
89	Burst 2 error fixed.	mihad	7735d 14h	/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7741d 13h	/
87	Updated acording to RTL changes.	mihad	7753d 11h	/
86	Entered the option to disable no response counter in wb master.	mihad	7753d 11h	/