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Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7885d 10h /
105 Wrong pci_bridge32.v file included in the project! mihad 7890d 17h /
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7890d 20h /
103 Added test application and modified files to support it. mihad 7937d 17h /
102 Cleanup! mihad 7937d 17h /
101 Added simulation files. mihad 7937d 17h /
100 Cleanup! mihad 7937d 17h /
99 Cleanup! mihad 7937d 17h /
98 Cleanup. mihad 7937d 17h /
97 Doing a little bit of cleanup. mihad 7937d 17h /
96 Update! mihad 7937d 18h /
95 Removed this file, because it was too large - long download time. mihad 7937d 18h /
94 Changed one critical PCI bus signal logic. mihad 7937d 18h /
93 Added a test application! mihad 7938d 01h /
92 Update! mihad 7938d 01h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7973d 15h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7973d 15h /
89 Burst 2 error fixed. mihad 8009d 16h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 8015d 15h /
87 Updated acording to RTL changes. mihad 8027d 12h /

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