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Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7725d 08h /
105 Wrong pci_bridge32.v file included in the project! mihad 7730d 15h /
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7730d 17h /
103 Added test application and modified files to support it. mihad 7777d 14h /
102 Cleanup! mihad 7777d 15h /
101 Added simulation files. mihad 7777d 15h /
100 Cleanup! mihad 7777d 15h /
99 Cleanup! mihad 7777d 15h /
98 Cleanup. mihad 7777d 15h /
97 Doing a little bit of cleanup. mihad 7777d 15h /
96 Update! mihad 7777d 15h /
95 Removed this file, because it was too large - long download time. mihad 7777d 15h /
94 Changed one critical PCI bus signal logic. mihad 7777d 15h /
93 Added a test application! mihad 7777d 23h /
92 Update! mihad 7777d 23h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7813d 13h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7813d 13h /
89 Burst 2 error fixed. mihad 7849d 13h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7855d 12h /
87 Updated acording to RTL changes. mihad 7867d 10h /

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