URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 54

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Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7979d 02h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7979d 06h	/
52	Oops, never before noticed that OC header is missing	mihad	7979d 10h	/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7979d 10h	/
50	Got rid of undef directives	mihad	7982d 02h	/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7982d 02h	/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7982d 03h	/
47	Known issues repaired	mihad	7982d 08h	/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7987d 03h	/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7988d 08h	/
44	Added for testing of Configuration Cycles Type 1	mihad	7988d 09h	/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7988d 09h	/
42	Removed out of date files	mihad	8000d 09h	/
41	This commit was manufactured by cvs2svn to create tag 'rel_00'.		8079d 00h	/
40	From these Wrod files PDF were created - added future improvements	tadej	8079d 00h	/
39	File not needed	tadej	8079d 01h	/
38	This file is not needed	tadej	8079d 04h	/
37	These files are not needed any more	tadej	8079d 04h	/
36	* empty log message *	tadej	8079d 04h	/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8133d 12h	/

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Subversion Repositories pci

[/] - Rev 54

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