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Rev	Log message	Author	Age	Path
62	Added BIST signals for RAMs.	mihad	8062d 02h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8070d 02h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8070d 02h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8070d 03h	/
58	Removed all logic from asynchronous reset network	mihad	8075d 03h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8075d 09h	/
56	Number of state bits define was removed	mihad	8076d 00h	/
55	Changed state machine encoding to true one-hot	mihad	8076d 01h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8109d 02h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8109d 06h	/
52	Oops, never before noticed that OC header is missing	mihad	8109d 10h	/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8109d 10h	/
50	Got rid of undef directives	mihad	8112d 02h	/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8112d 02h	/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8112d 02h	/
47	Known issues repaired	mihad	8112d 08h	/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8117d 02h	/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8118d 08h	/
44	Added for testing of Configuration Cycles Type 1	mihad	8118d 08h	/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8118d 08h	/

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[/] - Rev 62

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