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Rev	Log message	Author	Age	Path
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7933d 12h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7936d 13h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7936d 13h	/
73	Bug fixes, testcases added.	mihad	7936d 13h	/
72	* empty log message *	mihad	7983d 17h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7991d 08h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		8028d 16h	/
69	Changed BIST signal names etc..	mihad	8028d 16h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8032d 01h	/
67	Changed BIST signals for RAMs.	tadejm	8032d 06h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8035d 17h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8038d 15h	/
64	The testcase I just added in previous revision repaired	mihad	8038d 17h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8038d 19h	/
62	Added BIST signals for RAMs.	mihad	8041d 12h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8049d 12h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8049d 12h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8049d 13h	/
58	Removed all logic from asynchronous reset network	mihad	8054d 13h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8054d 19h	/

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[/] - Rev 76

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