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Rev	Log message	Author	Age	Path
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7823d 05h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7826d 06h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7826d 06h	/
73	Bug fixes, testcases added.	mihad	7826d 06h	/
72	* empty log message *	mihad	7873d 10h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7881d 02h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7918d 09h	/
69	Changed BIST signal names etc..	mihad	7918d 09h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7921d 19h	/
67	Changed BIST signals for RAMs.	tadejm	7922d 00h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 10h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 08h	/
64	The testcase I just added in previous revision repaired	mihad	7928d 10h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 12h	/
62	Added BIST signals for RAMs.	mihad	7931d 05h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7939d 05h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 05h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 06h	/
58	Removed all logic from asynchronous reset network	mihad	7944d 06h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7944d 12h	/

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[/] - Rev 76

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