URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 76

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	8076d 22h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	8079d 23h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		8080d 00h	/
73	Bug fixes, testcases added.	mihad	8080d 00h	/
72	* empty log message *	mihad	8127d 03h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	8134d 19h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		8172d 03h	/
69	Changed BIST signal names etc..	mihad	8172d 03h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8175d 12h	/
67	Changed BIST signals for RAMs.	tadejm	8175d 17h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8179d 03h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8182d 01h	/
64	The testcase I just added in previous revision repaired	mihad	8182d 04h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8182d 06h	/
62	Added BIST signals for RAMs.	mihad	8184d 22h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8192d 22h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8192d 22h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8193d 00h	/
58	Removed all logic from asynchronous reset network	mihad	8198d 00h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8198d 06h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] - Rev 76

Filtering Options