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Rev Log message Author Age Path
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 8073d 23h /
79 Updated. mihad 8073d 23h /
78 Old files with wrong names removed. mihad 8073d 23h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 8073d 23h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 8076d 22h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 8079d 23h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 8080d 00h /
73 Bug fixes, testcases added. mihad 8080d 00h /
72 *** empty log message *** mihad 8127d 03h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 8134d 19h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8172d 03h /
69 Changed BIST signal names etc.. mihad 8172d 03h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8175d 12h /
67 Changed BIST signals for RAMs. tadejm 8175d 17h /
66 Changed empty status generation in pciw_fifo_control.v mihad 8179d 03h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8182d 01h /
64 The testcase I just added in previous revision repaired mihad 8182d 04h /
63 Added additional testcase and changed rst name in BIST to trst mihad 8182d 06h /
62 Added BIST signals for RAMs. mihad 8184d 22h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8192d 22h /

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