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Rev Log message Author Age Path
95 Removed this file, because it was too large - long download time. mihad 7820d 19h /
94 Changed one critical PCI bus signal logic. mihad 7820d 19h /
93 Added a test application! mihad 7821d 02h /
92 Update! mihad 7821d 03h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7856d 16h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7856d 16h /
89 Burst 2 error fixed. mihad 7892d 17h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7898d 16h /
87 Updated acording to RTL changes. mihad 7910d 13h /
86 Entered the option to disable no response counter in wb master. mihad 7910d 14h /
85 Changed Vendor ID defines. mihad 7910d 18h /
84 Changed vendor ID. mihad 7914d 12h /
83 Cleaned up the code. No functional changes. mihad 7939d 11h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7953d 07h /
81 Updated synchronization in top level fifo modules. mihad 7953d 07h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7956d 12h /
79 Updated. mihad 7956d 12h /
78 Old files with wrong names removed. mihad 7956d 12h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7956d 12h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7959d 12h /

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