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17 Very hacky code to read paper tape files.

Isim reads integers as 32-bit signed little endian,
so we split that into the constituent bytes.

Simulation has now managed to use our preloaded
readin program to read the RIM of same program,
which contains another type of loader (with
checksumming), which read the program in again.
That's a lot of work for no real progress, but
the computer loads code.

To do: hardwired logic read in mode, tool to
feed RIM files to hardware, possibly a way to
load new tapes in simulation.		 yannv 2783d 05h /
16 Test data input for oscilloscope. Draws a circle. yannv 2783d 10h /
15 Rust oscilloscope: thread for async input yannv 2783d 10h /
14 Streaming data input in Rust oscilloscope.

Next up: Non-blocking input.		 yannv 2783d 10h /
13 Proof of concept Rust+Glium XY oscilloscope code.

To do: add input capability and proper time keeping.		 yannv 2784d 07h /
12 Proof of concept XY plotting in HTML canvas

Performance on my workstation is just about fast enough.
Work on a means of feeding points in.		 yannv 2784d 11h /
11 Rough xy oscilloscope display program.

Not actually usable, way too slow.		 yannv 2786d 02h /
10 testtop: use a uart to send serial data yannv 2786d 05h /
9 Avoid unsigned port for PC. yannv 2786d 06h /
8 Avoid inout signal. yannv 2786d 06h /
7 Typo fix. yannv 2786d 06h /
6 Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline.
Note that XST fails to create dual-port RAM if write data on one port is constant!
Next step is to use generic_dpram from opencores common.		 yannv 5014d 09h /
5 Add _i and _o suffixes to ports. yannv 5014d 10h /
4 Filled in some comments in vector2scanline.v.
My very first Verilog module, bear with me.		 yannv 5027d 05h /
3 Unpacked source code for further development in svn. yannv 5027d 05h /
2 Added Mercurial bundle of pre-subversion source code. yannv 5027d 05h /
1 The project and the structure was created root 5028d 07h /

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