URL https://opencores.org/ocsvn/pdp1/pdp1/trunk

Subversion Repositories pdp1

[/] - Rev 9

Rev	Log message	Author	Age	Path
9	Avoid unsigned port for PC.	yannv	2786d 12h	/
8	Avoid inout signal.	yannv	2786d 12h	/
7	Typo fix.	yannv	2786d 12h	/
6	Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline. Note that XST fails to create dual-port RAM if write data on one port is constant! Next step is to use generic_dpram from opencores common.	yannv	5014d 15h	/
5	Add _i and _o suffixes to ports.	yannv	5014d 16h	/
4	Filled in some comments in vector2scanline.v. My very first Verilog module, bear with me.	yannv	5027d 11h	/
3	Unpacked source code for further development in svn.	yannv	5027d 11h	/
2	Added Mercurial bundle of pre-subversion source code.	yannv	5027d 11h	/
1	The project and the structure was created	root	5028d 13h	/