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Rev Log message Author Age Path
11 Changed read task to capture data at rising edge of clock rehayes 5671d 05h /
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5672d 08h /
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5678d 01h /
8 Fix ack signal in testbench rehayes 5678d 02h /
7 Reflection of minor corrections rehayes 5682d 08h /
6 Reflection of minor corrections rehayes 5682d 08h /
5 rehayes 5720d 04h /
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5720d 04h /
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5720d 04h /
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5720d 05h /
1 The project was created and the structure was created root 5720d 19h /

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