URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] - Rev 17

Rev	Log message	Author	Age	Path
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5295d 11h	/
16	Added master error counter variable, added simulation timout limit	rehayes	5406d 13h	/
15	Fix blocking assigment	rehayes	5434d 14h	/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5503d 12h	/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5533d 16h	/
12	Fixed for single cycle reads	rehayes	5534d 11h	/
11	Changed read task to capture data at rising edge of clock	rehayes	5534d 11h	/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5535d 14h	/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5541d 07h	/
8	Fix ack signal in testbench	rehayes	5541d 08h	/
7	Reflection of minor corrections	rehayes	5545d 13h	/
6	Reflection of minor corrections	rehayes	5545d 13h	/
5		rehayes	5583d 09h	/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5583d 10h	/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5583d 10h	/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5583d 10h	/
1	The project was created and the structure was created	root	5584d 01h	/