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Rev Log message Author Age Path
20 minor update for timing constraint sugestions. rehayes 5407d 14h /
19 Minor change to add parameter to pit instance rehayes 5407d 15h /
18 Traded 16 data registers for 3 address registers when wait states are enabled. rehayes 5407d 17h /
17 Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle. rehayes 5421d 14h /
16 Added master error counter variable, added simulation timout limit rehayes 5532d 17h /
15 Fix blocking assigment rehayes 5560d 17h /
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5629d 15h /
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5659d 19h /
12 Fixed for single cycle reads rehayes 5660d 14h /
11 Changed read task to capture data at rising edge of clock rehayes 5660d 14h /
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5661d 17h /
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5667d 10h /
8 Fix ack signal in testbench rehayes 5667d 11h /
7 Reflection of minor corrections rehayes 5671d 17h /
6 Reflection of minor corrections rehayes 5671d 17h /
5 rehayes 5709d 13h /
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5709d 13h /
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5709d 13h /
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5709d 13h /
1 The project was created and the structure was created root 5710d 04h /

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