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Rev Log message Author Age Path
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7663d 21h /
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.
rhoads 7663d 21h /
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7663d 21h /
111 Updated to work with new convert.exe which updates opcodes to set $4, $5, and $sp. rhoads 7663d 21h /
110 support > 64kb memory with bss_start, bss_end, sp rhoads 7937d 17h /
109 support > 64kb memory with bss_start, bss_end, and sp rhoads 7937d 17h /
108 changed interrupt vector from 0x30 to 0x3c rhoads 7937d 17h /
107 merged rising_edge(clk) statements rhoads 7937d 17h /
106 better test mem_pause rhoads 7940d 20h /
105 better test mem_pause rhoads 7940d 20h /
104 use getchar() instead of getch() to be gcc friendly rhoads 7941d 19h /
103 shorten similation times rhoads 7941d 19h /
102 permit testing mem_pause rhoads 7941d 19h /
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7941d 19h /
100 test mult(a,-b) rhoads 8083d 18h /
99 correct upper 32-bits for mult(-1,-1) rhoads 8083d 18h /
98 Fix size of GENERIC ram. rhoads 8088d 17h /
97 added documentation rhoads 8152d 22h /
96 Simplify take_branch rhoads 8187d 00h /
95 register mem_write and mem_byte_sel for speed calculations rhoads 8187d 00h /

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