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Rev	Log message	Author	Age	Path
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7373d 19h	/
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7440d 20h	/
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7504d 20h	/
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7516d 09h	/
120	Make generics "GENERIC"	rhoads	7516d 09h	/
119	Opcodes from count.c	rhoads	7554d 20h	/
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 20h	/
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 20h	/
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 20h	/
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7554d 20h	/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7554d 20h	/
113	Matthias Grunewald's bug fixes: Branch and compare instructions didn't interpret immediate as signed.	rhoads	7554d 20h	/
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 20h	/
111	Updated to work with new convert.exe which updates opcodes to set $4, $5, and $sp.	rhoads	7554d 20h	/
110	support > 64kb memory with bss_start, bss_end, sp	rhoads	7828d 16h	/
109	support > 64kb memory with bss_start, bss_end, and sp	rhoads	7828d 16h	/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7828d 16h	/
107	merged rising_edge(clk) statements	rhoads	7828d 16h	/
106	better test mem_pause	rhoads	7831d 19h	/
105	better test mem_pause	rhoads	7831d 19h	/

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[/] - Rev 124

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