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Rev	Log message	Author	Age	Path
133	Fixed bug when MIPS executable compiled under Linux. Added lots of spaces	rhoads	7188d 12h	/
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7327d 10h	/
131	Changed "GENERIC" to "DEFAULT" to be Xilinx friendly.	rhoads	7327d 10h	/
130	Added better spacing	rhoads	7327d 10h	/
129	Added reset_in to sensitivity list	rhoads	7346d 10h	/
128	Reset all registers, constants now upper case.	rhoads	7464d 21h	/
127	This commit was manufactured by cvs2svn to create tag 'V2_1'.		7483d 11h	/
126	Added note that CC is for x86 and gmake has problems with MIPS gcc libraries.	rhoads	7483d 11h	/
125	Fixed pc_source_type comment.	rhoads	7483d 11h	/
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7483d 11h	/
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7550d 11h	/
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7614d 12h	/
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7626d 00h	/
120	Make generics "GENERIC"	rhoads	7626d 00h	/
119	Opcodes from count.c	rhoads	7664d 11h	/
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7664d 11h	/
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7664d 11h	/
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7664d 11h	/
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7664d 11h	/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7664d 11h	/

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[/] - Rev 133

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