OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.
skordal 3315d 10h /
25 Add placeholder cache modules and a wishbone arbiter skordal 3317d 14h /
24 Remove unused STRINGIFY macros skordal 3318d 03h /
23 Create branch to use for implementing a cache skordal 3318d 03h /
22 Fix the potato_get_badvaddr() macro skordal 3318d 04h /
21 Upgrade the example design to use a 60 MHz system clock skordal 3318d 04h /
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.
skordal 3318d 04h /
19 SHA256 benchmark: allow compiler to inline at will skordal 3318d 04h /
18 instr_misalign_check: add do_jump to sensitivity list skordal 3320d 04h /
17 Improve detection of unaligned instructions skordal 3324d 11h /
16 Correct grammar in source code comment skordal 3324d 11h /
15 SHA256 benchmark: fix Makefile syntax error skordal 3331d 04h /
14 Improve detection of invalid instructions skordal 3331d 05h /
13 Add SHA256 benchmark code skordal 3331d 09h /
12 Update example design with correct bug-report URL and testbenches skordal 3331d 11h /
11 Correct FIFO file header skordal 3331d 12h /
10 Add missing FIFO module skordal 3336d 05h /
9 Remove dependency on a non-existent target in the Makefile skordal 3336d 05h /
8 Clarify instruction ROM naming in the example design README skordal 3343d 08h /
7 Add test design for the Nexys 4 board from Digilent skordal 3343d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.