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Rev Log message Author Age Path
54 Update benchmarks to work with supervisor spec v1.7 skordal 3395d 03h /
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3397d 04h /
52 Correct .data section of sw-jal test skordal 3397d 04h /
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3397d 04h /
50 Update test environment to the new supervisor ISA skordal 3409d 04h /
49 Correct spelling of "privileged" skordal 3419d 04h /
48 Create branch for upgrading to the new privileged ISA skordal 3419d 04h /
47 Tag version 0.1 of the Potato Processor skordal 3419d 12h /
46 Remove branch: cache-playground skordal 3422d 06h /
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3422d 06h /
44 Add instruction cache and use the WB adapter as dmem interface skordal 3422d 06h /
43 Improve instruction fetch logic skordal 3422d 06h /
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3422d 06h /
41 Make continouous status register reads asynchronous skordal 3422d 06h /
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3422d 06h /
39 Disable IRQs when handling exceptions skordal 3422d 06h /
38 Add "Hello World" test application skordal 3422d 07h /
37 Add macro to set the TOHOST register from C code skordal 3422d 07h /
36 Ensure correct read of CSR after stall skordal 3422d 08h /
35 Prevent jumping/branching when stalling skordal 3422d 08h /

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