URL https://opencores.org/ocsvn/r2000/r2000/trunk

Subversion Repositories r2000

[/] - Rev 9

Rev	Log message	Author	Age	Path
9	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	6125d 12h	/
8	Enhancement of the "Controler specification doc".	ameziti	6128d 12h	/
7	Add Pipeline Controler specification documentation.	ameziti	6129d 11h	/
6	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	6129d 13h	/
5	Remove the Multiple Arithmetic Unit fonction. - The Pipeline must stall when Mult/Div unit is busy. - Whether there's a mflo or mfhi. - see `define MULTIPLE_ALU	ameziti	6130d 10h	/
4	Add Soc Image in the Specification documentation	ameziti	6151d 13h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		6152d 21h	/
2	First Import the project on the opencores.org CVS server	ameziti	6152d 21h	/
1	Standard project directories initialized by cvs2svn.		6152d 21h	/