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Rev Log message Author Age Path
119 382 LEs Adder, RTL viewer Check Ok jguarin2002 4730d 20h /
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 4731d 03h /
117 Official reduction achieved 12% jguarin2002 4731d 09h /
116 Official Reduction is 7%: Adder 420 logic cells, trying to reach out at least 20 less cells jguarin2002 4731d 10h /
115 Official Reduction is about 7% jguarin2002 4731d 10h /
114 lost of time.. jguarin2002 4732d 09h /
113 Will end this tomorrow for sure.... anyway i dont think i will got something below 400... jguarin2002 4737d 23h /
112 99.7%... almost there jguarin2002 4738d 01h /
111 99% of work done jguarin2002 4738d 10h /
110 Chopchop 99% jguarin2002 4739d 05h /
109 Still working on adder, almost there..... jguarin2002 4739d 22h /
108 Ongoing work... 75% jguarin2002 4740d 16h /
107 working working and working... jguarin2002 4741d 08h /
106 Optimizing Adder.... at a very slow pace... Got to rush jguarin2002 4745d 16h /
105 Control... jguarin2002 4756d 15h /
104 Square Root and inversion support jguarin2002 4762d 00h /
103 Square Root Ok jguarin2002 4762d 07h /
102 FP additions done jguarin2002 4762d 08h /
101 theres a new command to offset the first address in the file jguarin2002 4763d 22h /
100 Additions Ended jguarin2002 4763d 22h /

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