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Rev Log message Author Age Path
121 taking out std_logic_arith from sight.... no conversions allowed jguarin2002 4735d 01h /
120 Beta 0 Adder LCELLS 373 jguarin2002 4741d 00h /
119 382 LEs Adder, RTL viewer Check Ok jguarin2002 4741d 06h /
118 fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32 jguarin2002 4741d 13h /
117 Official reduction achieved 12% jguarin2002 4741d 19h /
116 Official Reduction is 7%: Adder 420 logic cells, trying to reach out at least 20 less cells jguarin2002 4741d 20h /
115 Official Reduction is about 7% jguarin2002 4741d 20h /
114 lost of time.. jguarin2002 4742d 19h /
113 Will end this tomorrow for sure.... anyway i dont think i will got something below 400... jguarin2002 4748d 09h /
112 99.7%... almost there jguarin2002 4748d 11h /
111 99% of work done jguarin2002 4748d 20h /
110 Chopchop 99% jguarin2002 4749d 14h /
109 Still working on adder, almost there..... jguarin2002 4750d 08h /
108 Ongoing work... 75% jguarin2002 4751d 02h /
107 working working and working... jguarin2002 4751d 18h /
106 Optimizing Adder.... at a very slow pace... Got to rush jguarin2002 4756d 02h /
105 Control... jguarin2002 4767d 01h /
104 Square Root and inversion support jguarin2002 4772d 10h /
103 Square Root Ok jguarin2002 4772d 17h /
102 FP additions done jguarin2002 4772d 17h /

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