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Rev	Log message	Author	Age	Path
143	working on result queue sync decoding signals	jguarin2002	4715d 07h	/
142	Additions for the State Machine	jguarin2002	4720d 05h	/
141	Syncing: its awful work: input adresses decoded to include the instructions queue also....	jguarin2002	4787d 07h	/
140	Syncing: its awful work.....	jguarin2002	4787d 13h	/
139	Sync	jguarin2002	4799d 03h	/
138	enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes	jguarin2002	4803d 18h	/
137	Syncing with enables and eleminated all the register outputs since none block should carry on a register output	jguarin2002	4809d 19h	/
136	gogogo	jguarin2002	4812d 06h	/
135	Correction on conectiveness of Datapath Control...	jguarin2002	4816d 06h	/
134	State Machine, for addressing counting, internal writing & reading control and interruption generation	jguarin2002	4818d 02h	/
133	Added the instructions queue	jguarin2002	4819d 18h	/
132	There was amiss in the cross product datapath decoder	jguarin2002	4823d 13h	/
131	Post RTL check on memblock	jguarin2002	4823d 19h	/
130	RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos	jguarin2002	4824d 14h	/
129	Memory Block: Identified the four circuits: External Write, External Read, Internal Write, Internal Read.	jguarin2002	4830d 03h	/
128	Memblock, for input registers and intermezzo results queues: normfifox26x96 & dpfifo9x64, dpc is done	jguarin2002	4837d 05h	/
127	Datapath Control Done	jguarin2002	4837d 17h	/
126	dpc: Datapath Control Finished..... test it	jguarin2002	4841d 12h	/
125	DPC the result is just left	jguarin2002	4842d 06h	/
124	lost....	jguarin2002	4846d 06h	/

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[/] - Rev 143

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