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Rev	Log message	Author	Age	Path
147	Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified.	jguarin2002	4691d 05h	/
146	Interruption Machine	jguarin2002	4698d 23h	/
145	State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig	jguarin2002	4703d 12h	/
144	The commented part of DPC was erased, and no longer needed.	jguarin2002	4710d 16h	/
143	working on result queue sync decoding signals	jguarin2002	4715d 08h	/
142	Additions for the State Machine	jguarin2002	4720d 07h	/
141	Syncing: its awful work: input adresses decoded to include the instructions queue also....	jguarin2002	4787d 08h	/
140	Syncing: its awful work.....	jguarin2002	4787d 14h	/
139	Sync	jguarin2002	4799d 04h	/
138	enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes	jguarin2002	4803d 19h	/
137	Syncing with enables and eleminated all the register outputs since none block should carry on a register output	jguarin2002	4809d 20h	/
136	gogogo	jguarin2002	4812d 07h	/
135	Correction on conectiveness of Datapath Control...	jguarin2002	4816d 08h	/
134	State Machine, for addressing counting, internal writing & reading control and interruption generation	jguarin2002	4818d 03h	/
133	Added the instructions queue	jguarin2002	4819d 19h	/
132	There was amiss in the cross product datapath decoder	jguarin2002	4823d 15h	/
131	Post RTL check on memblock	jguarin2002	4823d 21h	/
130	RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos	jguarin2002	4824d 15h	/
129	Memory Block: Identified the four circuits: External Write, External Read, Internal Write, Internal Read.	jguarin2002	4830d 04h	/
128	Memblock, for input registers and intermezzo results queues: normfifox26x96 & dpfifo9x64, dpc is done	jguarin2002	4837d 06h	/

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[/] - Rev 147

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