OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] - Rev 153

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
153 last modifications for tb_compiler.py compliance jguarin2002 4471d 06h /
152 Test bench oriented modifications jguarin2002 4475d 07h /
151 Previous Work to generate test benching jguarin2002 4534d 03h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4548d 00h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4548d 03h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4548d 04h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4550d 16h /
146 Interruption Machine jguarin2002 4558d 10h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4563d 00h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4570d 03h /
143 working on result queue sync decoding signals jguarin2002 4574d 19h /
142 Additions for the State Machine jguarin2002 4579d 18h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4646d 19h /
140 Syncing: its awful work..... jguarin2002 4647d 01h /
139 Sync jguarin2002 4658d 15h /
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4663d 06h /
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4669d 07h /
136 gogogo jguarin2002 4671d 18h /
135 Correction on conectiveness of Datapath Control... jguarin2002 4675d 19h /
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 4677d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.