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Rev Log message Author Age Path
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4609d 03h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4611d 19h /
153 last modifications for tb_compiler.py compliance jguarin2002 4611d 19h /
152 Test bench oriented modifications jguarin2002 4615d 20h /
151 Previous Work to generate test benching jguarin2002 4674d 16h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4688d 13h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4688d 16h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4688d 17h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4691d 05h /
146 Interruption Machine jguarin2002 4698d 23h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4703d 13h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4710d 16h /
143 working on result queue sync decoding signals jguarin2002 4715d 08h /
142 Additions for the State Machine jguarin2002 4720d 07h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4787d 08h /
140 Syncing: its awful work..... jguarin2002 4787d 14h /
139 Sync jguarin2002 4799d 04h /
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4803d 19h /
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4809d 20h /
136 gogogo jguarin2002 4812d 07h /

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