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Rev Log message Author Age Path
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4487d 20h /
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4488d 08h /
156 Test Bench Beta 0.1 jguarin2002 4488d 20h /
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4491d 20h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4494d 12h /
153 last modifications for tb_compiler.py compliance jguarin2002 4494d 12h /
152 Test bench oriented modifications jguarin2002 4498d 13h /
151 Previous Work to generate test benching jguarin2002 4557d 09h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4571d 06h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4571d 09h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4571d 10h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4573d 22h /
146 Interruption Machine jguarin2002 4581d 16h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4586d 06h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4593d 09h /
143 working on result queue sync decoding signals jguarin2002 4598d 01h /
142 Additions for the State Machine jguarin2002 4603d 00h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4670d 01h /
140 Syncing: its awful work..... jguarin2002 4670d 07h /
139 Sync jguarin2002 4681d 21h /

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