OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] - Rev 162

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
162 Señales para evaluar en simulación funcional jguarin2002 4550d 13h /
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4552d 04h /
160 Corrections derived from simulation debugging jguarin2002 4556d 20h /
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4558d 06h /
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4558d 10h /
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4558d 22h /
156 Test Bench Beta 0.1 jguarin2002 4559d 10h /
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4562d 10h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4565d 02h /
153 last modifications for tb_compiler.py compliance jguarin2002 4565d 02h /
152 Test bench oriented modifications jguarin2002 4569d 04h /
151 Previous Work to generate test benching jguarin2002 4628d 00h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4641d 21h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4642d 00h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4642d 00h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4644d 12h /
146 Interruption Machine jguarin2002 4652d 06h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4656d 20h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4664d 00h /
143 working on result queue sync decoding signals jguarin2002 4668d 16h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.