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Rev Log message Author Age Path
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4543d 16h /
180 Documentos de diseño y documento final jguarin2002 4543d 16h /
179 light change on code readbility for Datapath Control hardware description hdl file jguarin2002 4544d 13h /
178 QSYS SOPC Raytrac component.... jguarin2002 4568d 04h /
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4568d 04h /
176 Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code jguarin2002 4580d 02h /
175 Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. jguarin2002 4580d 02h /
174 Comment tweaking... its the same RTL anyway jguarin2002 4580d 02h /
173 Added a procedure to support vectorblock03 type variables rendering after testbench execution jguarin2002 4580d 02h /
172 Results fifo writing signals added to the testbench jguarin2002 4580d 02h /
171 After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested jguarin2002 4580d 02h /
170 Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder jguarin2002 4580d 02h /
169 Long Stupid, version of a 32 bit floating point I3E754 Adder jguarin2002 4580d 03h /
168 Added a display function for vectorblock02 jguarin2002 4582d 16h /
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4582d 16h /
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4583d 03h /
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4583d 12h /
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4584d 13h /
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4584d 15h /
162 Señales para evaluar en simulación funcional jguarin2002 4584d 15h /

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