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Rev Log message Author Age Path
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4553d 07h /
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4553d 14h /
188 Fitting Report jguarin2002 4554d 21h /
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4554d 21h /
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4554d 21h /
185 Well mulblock was a void inside file.... jguarin2002 4555d 10h /
184 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4555d 14h /
183 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4555d 14h /
182 Sobre la sincronización del RayTrac al escribir instrucciones y operandos. Pagina 29 y 31. jguarin2002 4555d 15h /
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4555d 22h /
180 Documentos de diseño y documento final jguarin2002 4555d 22h /
179 light change on code readbility for Datapath Control hardware description hdl file jguarin2002 4556d 19h /
178 QSYS SOPC Raytrac component.... jguarin2002 4580d 10h /
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4580d 10h /
176 Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code jguarin2002 4592d 09h /
175 Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. jguarin2002 4592d 09h /
174 Comment tweaking... its the same RTL anyway jguarin2002 4592d 09h /
173 Added a procedure to support vectorblock03 type variables rendering after testbench execution jguarin2002 4592d 09h /
172 Results fifo writing signals added to the testbench jguarin2002 4592d 09h /
171 After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested jguarin2002 4592d 09h /

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