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Rev Log message Author Age Path
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4555d 07h /
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4555d 07h /
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4559d 15h /
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4559d 22h /
188 Fitting Report jguarin2002 4561d 05h /
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4561d 05h /
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4561d 05h /
185 Well mulblock was a void inside file.... jguarin2002 4561d 19h /
184 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4561d 23h /
183 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4561d 23h /
182 Sobre la sincronización del RayTrac al escribir instrucciones y operandos. Pagina 29 y 31. jguarin2002 4562d 00h /
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4562d 07h /
180 Documentos de diseño y documento final jguarin2002 4562d 07h /
179 light change on code readbility for Datapath Control hardware description hdl file jguarin2002 4563d 04h /
178 QSYS SOPC Raytrac component.... jguarin2002 4586d 19h /
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4586d 19h /
176 Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code jguarin2002 4598d 17h /
175 Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. jguarin2002 4598d 17h /
174 Comment tweaking... its the same RTL anyway jguarin2002 4598d 18h /
173 Added a procedure to support vectorblock03 type variables rendering after testbench execution jguarin2002 4598d 18h /

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