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Rev Log message Author Age Path
210 Document advance..... towards dma oriented raytrac jguarin2002 4500d 01h /
209 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
208 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
207 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
206 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
205 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
204 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
203 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
202 Working towards a DMA oriented RayTRac jguarin2002 4500d 01h /
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4500d 01h /
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4500d 01h /
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4516d 07h /
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4516d 07h /
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4526d 08h /
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4529d 19h /
195 Document advance and changes in the design jguarin2002 4532d 16h /
194 Work In Progress jguarin2002 4547d 22h /
193 WIP: Main Document jguarin2002 4548d 19h /
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4549d 07h /
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4549d 07h /

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