| Rev |
Log message |
Author |
Age |
Path |
| 227 |
Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. |
jguarin2002 |
4477d 19h |
/ |
| 226 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4477d 20h |
/ |
| 225 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4477d 21h |
/ |
| 224 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4477d 22h |
/ |
| 223 |
Reportes para NS_JULI_SDF_ASM_AP_DMA_130812_21028 |
jguarin2002 |
4484d 20h |
/ |
| 222 |
documento en un 55\% |
jguarin2002 |
4484d 20h |
/ |
| 221 |
The change in sqrt and inv is about the path of the files with the data memory. dpc has been changed by ap_n_dpc and there was an error on RayTrac related to the load sync chain: the loading of Dot product Operation was being carried out as if it was an unary operation rather than a two operands operation |
jguarin2002 |
4487d 06h |
/ |
| 220 |
ap_n_dpc.vhd es el RTL que integra DataPathControl y ArithPipeLine |
jguarin2002 |
4487d 07h |
/ |
| 219 |
RayTrac: Non tested and witouh TSE |
jguarin2002 |
4487d 08h |
/ |
| 218 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : SOPC Library TCL scrip, load it into the Altera Project |
jguarin2002 |
4487d 12h |
/ |
| 217 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used |
jguarin2002 |
4487d 12h |
/ |
| 216 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4488d 04h |
/ |
| 215 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4488d 04h |
/ |
| 214 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4488d 04h |
/ |
| 213 |
Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) |
jguarin2002 |
4488d 04h |
/ |
| 212 |
DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. |
jguarin2002 |
4488d 04h |
/ |
| 211 |
Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! |
jguarin2002 |
4488d 04h |
/ |
| 210 |
Document advance..... towards dma oriented raytrac |
jguarin2002 |
4499d 17h |
/ |
| 209 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4499d 17h |
/ |
| 208 |
Working towards a DMA oriented RayTRac |
jguarin2002 |
4499d 17h |
/ |
