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Rev Log message Author Age Path
60 Shifter circuit for Division Phase one done jguarin2002 4946d 23h /
59 Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt jguarin2002 4950d 05h /
58 Testbenching corrections..... jguarin2002 4960d 01h /
57 testbench verification AWFUL HORRIBLE BAD WRITTEN GREMLIN PROGRAM jguarin2002 4961d 00h /
56 Stop conditions..... jguarin2002 4968d 05h /
55 Unifying Testbench written files format...... jguarin2002 4968d 06h /
54 Unifying Testbench written files format...... jguarin2002 4968d 08h /
53 Improved TRACE_rom_contents.csv presentation jguarin2002 4975d 17h /
52 Working...... jguarin2002 4996d 16h /
51 There's now a descent testbench 2.0\!\!\! jguarin2002 5003d 16h /
50 There's now a descent testbench\!\!\! jguarin2002 5004d 21h /
49 Test bench ifs finally running jguarin2002 5005d 16h /
48 Developing first testbench.... also learning how to do it jguarin2002 5007d 13h /
47 Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation jguarin2002 5009d 00h /
46 simplified memory path jguarin2002 5009d 03h /
45 Magic is already written... now we shall set the testbench on fire\! jguarin2002 5010d 15h /
44 All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... jguarin2002 5011d 16h /
43 Nothing to say, just working on the Test Bench... jguarin2002 5012d 00h /
42 no comment no tb yet: jguarin2002 5012d 17h /
41 Ram for the massses\!\!\! jguarin2002 5015d 04h /

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