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Rev Log message Author Age Path
77 Now support for addition and substraction of A(7,10) component vectors jguarin2002 4927d 06h /
76 Upgrade para obtener una mantissa de 20 bits jguarin2002 4929d 04h /
75 Optimization done on matissa lenght for x**-1 and x**0.5, getting a longer mantissa of 20 bits instead one of 18 bits jguarin2002 4930d 23h /
74 On the rush, correct chip floor planning problem jguarin2002 4935d 17h /
73 Almost Ready Division and Square Root jguarin2002 4936d 21h /
72 Minor changes, is more a matter of format rather than anything... jguarin2002 4937d 10h /
71 RLshifterAlfa jguarin2002 4940d 03h /
70 RLshifterbeta++ jguarin2002 4940d 03h /
69 RLshifterbeta jguarin2002 4940d 05h /
68 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4940d 16h /
67 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4942d 18h /
66 tb.vhd moved to testbench directory jguarin2002 4944d 06h /
65 move memmaker to utils directory jguarin2002 4944d 06h /
64 Code split in directories like: sqrtdiv tb utils jguarin2002 4944d 06h /
63 square root function, from [sqrt(1.0),sqrt(2.0)). inverse function from [1/1.0, 1/2.0) jguarin2002 4944d 07h /
62 memaker correction..... check diff jguarin2002 4944d 07h /
61 Memory maker modified in order to support square root and inverse functions jguarin2002 4944d 08h /
60 Shifter circuit for Division Phase one done jguarin2002 4947d 02h /
59 Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt jguarin2002 4950d 08h /
58 Testbenching corrections..... jguarin2002 4960d 03h /

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