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Rev	Log message	Author	Age	Path
87	For the sake of easyness, mmp is called now mul2	jguarin2002	4914d 09h	/
86	For the sake of easyness, mmp is called now mul2	jguarin2002	4914d 09h	/
85	get doesnt fit anymore...	jguarin2002	4915d 00h	/
84	Floating Point Adders: (ema3,add3) is an a+b+c adder and (ema2,add2) is an a+b adder. Ema's are blocks to normalize the exponents and shift the mantissas as required, add's are blocks that make the mantissa addition and normalize the result again into a 32 bit IEEE float format	jguarin2002	4915d 00h	/
83	Only to have it as an example of what to do to sign a mantissa	jguarin2002	4915d 00h	/
82	FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd	jguarin2002	4917d 19h	/
81	Almost There	jguarin2002	4921d 17h	/
80	not a revision	jguarin2002	4922d 09h	/
79	I can't use a 20 bits mantissa.... eliminating optimization	jguarin2002	4926d 04h	/
78	Metamorphosis	jguarin2002	4933d 17h	/
77	Now support for addition and substraction of A(7,10) component vectors	jguarin2002	4934d 06h	/
76	Upgrade para obtener una mantissa de 20 bits	jguarin2002	4936d 04h	/
75	Optimization done on matissa lenght for x-1 and x0.5, getting a longer mantissa of 20 bits instead one of 18 bits	jguarin2002	4937d 23h	/
74	On the rush, correct chip floor planning problem	jguarin2002	4942d 17h	/
73	Almost Ready Division and Square Root	jguarin2002	4943d 21h	/
72	Minor changes, is more a matter of format rather than anything...	jguarin2002	4944d 10h	/
71	RLshifterAlfa	jguarin2002	4947d 03h	/
70	RLshifterbeta++	jguarin2002	4947d 03h	/
69	RLshifterbeta	jguarin2002	4947d 05h	/
68	On the rush cant explain what I did, but sure its about sqrtdiv	jguarin2002	4947d 16h	/

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[/] - Rev 87

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