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Rev Log message Author Age Path
14 Most issues solved, testbench issues remains. magro732 4121d 07h /
13 Timeouts are working. magro732 4124d 08h /
12 Backup of recent work, debugging new RioSerial. magro732 4135d 07h /
11 Receiver ready, transmitter is compiling. magro732 4135d 08h /
10 Branch to develop support for parallel symbols. magro732 4135d 08h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4176d 19h /
8 Adding signal descriptions in comments. magro732 4220d 09h /
7 Adding missing generic parameters to RioPacketBuffer. magro732 4307d 12h /
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4307d 14h /
5 Uploading primitive documentation. magro732 4314d 07h /
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4336d 20h /
3 Adding RioPacketBuffer and testbench. magro732 4337d 12h /
2 Adding RioSwitch and testbench. magro732 4337d 14h /
1 The project and the structure was created root 4338d 20h /

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