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Rev Log message Author Age Path
18 Making RioSerial entity the same as before+minor fixes. magro732 4117d 07h /
17 Removing latch and improving timing. magro732 4118d 08h /
16 Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing. magro732 4118d 08h /
15 All testcases are ok. Still needs some tweeks though. magro732 4122d 09h /
14 Most issues solved, testbench issues remains. magro732 4125d 08h /
13 Timeouts are working. magro732 4128d 09h /
12 Backup of recent work, debugging new RioSerial. magro732 4139d 08h /
11 Receiver ready, transmitter is compiling. magro732 4139d 09h /
10 Branch to develop support for parallel symbols. magro732 4139d 09h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4180d 20h /
8 Adding signal descriptions in comments. magro732 4224d 10h /
7 Adding missing generic parameters to RioPacketBuffer. magro732 4311d 13h /
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4311d 15h /
5 Uploading primitive documentation. magro732 4318d 08h /
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4340d 21h /
3 Adding RioPacketBuffer and testbench. magro732 4341d 13h /
2 Adding RioSwitch and testbench. magro732 4341d 15h /
1 The project and the structure was created root 4342d 21h /

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