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Subversion Repositories rio

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Rev Log message Author Age Path
19 Removing synthesis warnings. magro732 4197d 05h /
18 Making RioSerial entity the same as before+minor fixes. magro732 4198d 04h /
17 Removing latch and improving timing. magro732 4199d 04h /
16 Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing. magro732 4199d 05h /
15 All testcases are ok. Still needs some tweeks though. magro732 4203d 05h /
14 Most issues solved, testbench issues remains. magro732 4206d 05h /
13 Timeouts are working. magro732 4209d 05h /
12 Backup of recent work, debugging new RioSerial. magro732 4220d 04h /
11 Receiver ready, transmitter is compiling. magro732 4220d 05h /
10 Branch to develop support for parallel symbols. magro732 4220d 05h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4261d 16h /
8 Adding signal descriptions in comments. magro732 4305d 06h /
7 Adding missing generic parameters to RioPacketBuffer. magro732 4392d 10h /
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4392d 12h /
5 Uploading primitive documentation. magro732 4399d 04h /
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4421d 17h /
3 Adding RioPacketBuffer and testbench. magro732 4422d 09h /
2 Adding RioSwitch and testbench. magro732 4422d 11h /
1 The project and the structure was created root 4423d 17h /

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