URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] - Rev 28

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3736d 13h	/
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3738d 00h	/
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3898d 12h	/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3905d 05h	/
24	Changing errornous use statement.	magro732	3905d 06h	/
23	Tagging alpha release 2.0.0.	magro732	4021d 23h	/
22	Tagging release 1.0.0.	magro732	4021d 23h	/
21	Branching of a single symbol version of the new RioSerial.	magro732	4022d 00h	/
20	Adding software C-stack and matching VHDL modules.	magro732	4087d 02h	/
19	Removing synthesis warnings.	magro732	4112d 01h	/
18	Making RioSerial entity the same as before+minor fixes.	magro732	4113d 00h	/
17	Removing latch and improving timing.	magro732	4114d 01h	/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	4114d 01h	/
15	All testcases are ok. Still needs some tweeks though.	magro732	4118d 02h	/
14	Most issues solved, testbench issues remains.	magro732	4121d 01h	/
13	Timeouts are working.	magro732	4124d 02h	/
12	Backup of recent work, debugging new RioSerial.	magro732	4135d 01h	/
11	Receiver ready, transmitter is compiling.	magro732	4135d 01h	/
10	Branch to develop support for parallel symbols.	magro732	4135d 01h	/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4176d 13h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories rio

[/] - Rev 28

Filtering Options