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Subversion Repositories rio

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Rev Log message Author Age Path
28 Correcting bug in RioSwitch.vhd internal Wishbone interconnect.
Modifying an existing test case in TestRioSwitch.vhd to provoke the error.
magro732 3718d 00h /
27 Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled. magro732 3719d 11h /
26 Temporary checkin of parallelSymbols branch. It does not work yet. magro732 3879d 23h /
25 Correcting compiler errors in TestRioPcsUart.vhd magro732 3886d 17h /
24 Changing errornous use statement. magro732 3886d 17h /
23 Tagging alpha release 2.0.0. magro732 4003d 10h /
22 Tagging release 1.0.0. magro732 4003d 11h /
21 Branching of a single symbol version of the new RioSerial. magro732 4003d 11h /
20 Adding software C-stack and matching VHDL modules. magro732 4068d 13h /
19 Removing synthesis warnings. magro732 4093d 12h /
18 Making RioSerial entity the same as before+minor fixes. magro732 4094d 11h /
17 Removing latch and improving timing. magro732 4095d 12h /
16 Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing. magro732 4095d 12h /
15 All testcases are ok. Still needs some tweeks though. magro732 4099d 13h /
14 Most issues solved, testbench issues remains. magro732 4102d 12h /
13 Timeouts are working. magro732 4105d 13h /
12 Backup of recent work, debugging new RioSerial. magro732 4116d 12h /
11 Receiver ready, transmitter is compiling. magro732 4116d 12h /
10 Branch to develop support for parallel symbols. magro732 4116d 12h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4158d 00h /

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