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Rev	Log message	Author	Age	Path
100	- Signal clear_in was missing in sensitivity list.	cwalter	6424d 01h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6424d 01h	/
98	- Applied indenting tool.	cwalter	6424d 01h	/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6424d 02h	/
96	- SR register is now computed in ALU stage.	cwalter	6424d 02h	/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6424d 03h	/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6424d 03h	/
93	Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result.	jlechner	6424d 03h	/
92	Added logic for inserting a nop instruction when the pipeline is cleared.	jlechner	6424d 03h	/
91	- Computed new SR values from ALU result.	cwalter	6424d 03h	/
90	Added output signal for clearing all register locks when a branch instruction is executed. This is necessary because the id stage could have locked registers for an instruction that is cleared out of the pipeline due to the branch.	jlechner	6424d 03h	/
89	Added input signal for clearing all register locks.	jlechner	6424d 03h	/
88	- Added new patch for assembler.	cwalter	6424d 04h	/
87	no message	cwalter	6424d 04h	/
86	- Added new example for a more complex loop.	cwalter	6424d 04h	/
85	Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient branch immediately.	jlechner	6424d 06h	/
84	- PC value was wrong.	cwalter	6424d 06h	/
83	- sr_enable and lr_enable where incorrect.	cwalter	6424d 06h	/
82	- Updated drawings for memory.	cwalter	6424d 07h	/
81	- Changed to include barrel shifter.	cwalter	6424d 07h	/

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