URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 113

Rev	Log message	Author	Age	Path
113	Uart reset funkt	trinklhar	6511d 04h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6511d 05h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6513d 21h	/
110	- Added missing file to CVS.	cwalter	6514d 04h	/
109	- Assembler code for ST produced wrong instruction format.	cwalter	6514d 19h	/
108	no message	cwalter	6514d 19h	/
107	- Added new example for memory testing.	cwalter	6514d 20h	/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6514d 20h	/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6514d 20h	/
104	- Added missing signal dmem_data_in.	cwalter	6514d 20h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6514d 20h	/
102	changed data pitch	ustadler	6517d 01h	/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6517d 02h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6517d 02h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6517d 02h	/
98	- Applied indenting tool.	cwalter	6517d 02h	/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6517d 03h	/
96	- SR register is now computed in ALU stage.	cwalter	6517d 03h	/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6517d 03h	/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6517d 03h	/