URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 127

Rev	Log message	Author	Age	Path
127	Changed high active resets to low active ones.	jlechner	6473d 01h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6473d 08h	/
125	Fixed vhdl bugs	trinklhar	6473d 08h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6473d 08h	/
123	Removed UART again	trinklhar	6473d 09h	/
122	Removed UART again again	trinklhar	6473d 09h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6473d 09h	/
120	Added UART module to memory entity	trinklhar	6473d 09h	/
119	Uart wieder ausgebaut	trinklhar	6474d 04h	/
118	insert Uart address constant	trinklhar	6474d 04h	/
117	Uart im mem_stage	trinklhar	6474d 04h	/
116	writes to uart when write to reg 0	trinklhar	6475d 10h	/
115	* empty log message *	trinklhar	6476d 00h	/
114	Uart 0.3	trinklhar	6477d 04h	/
113	Uart reset funkt	trinklhar	6477d 05h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6477d 07h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6479d 23h	/
110	- Added missing file to CVS.	cwalter	6480d 05h	/
109	- Assembler code for ST produced wrong instruction format.	cwalter	6480d 21h	/
108	no message	cwalter	6480d 21h	/