URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 130

Rev	Log message	Author	Age	Path
130	Removed obsolete line	jlechner	6423d 17h	/
129	Sample assembler program for accessing uart	jlechner	6423d 17h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6423d 17h	/
127	Changed high active resets to low active ones.	jlechner	6423d 17h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6423d 23h	/
125	Fixed vhdl bugs	trinklhar	6423d 23h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6423d 23h	/
123	Removed UART again	trinklhar	6424d 00h	/
122	Removed UART again again	trinklhar	6424d 00h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6424d 00h	/
120	Added UART module to memory entity	trinklhar	6424d 00h	/
119	Uart wieder ausgebaut	trinklhar	6424d 19h	/
118	insert Uart address constant	trinklhar	6424d 19h	/
117	Uart im mem_stage	trinklhar	6424d 19h	/
116	writes to uart when write to reg 0	trinklhar	6426d 02h	/
115	* empty log message *	trinklhar	6426d 16h	/
114	Uart 0.3	trinklhar	6427d 20h	/
113	Uart reset funkt	trinklhar	6427d 21h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6427d 22h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6430d 14h	/