URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 131

Rev	Log message	Author	Age	Path
131	Changed high active resets to low active ones.	jlechner	6377d 23h	/
130	Removed obsolete line	jlechner	6378d 00h	/
129	Sample assembler program for accessing uart	jlechner	6378d 00h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6378d 00h	/
127	Changed high active resets to low active ones.	jlechner	6378d 00h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6378d 06h	/
125	Fixed vhdl bugs	trinklhar	6378d 06h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6378d 06h	/
123	Removed UART again	trinklhar	6378d 07h	/
122	Removed UART again again	trinklhar	6378d 07h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6378d 07h	/
120	Added UART module to memory entity	trinklhar	6378d 07h	/
119	Uart wieder ausgebaut	trinklhar	6379d 02h	/
118	insert Uart address constant	trinklhar	6379d 02h	/
117	Uart im mem_stage	trinklhar	6379d 02h	/
116	writes to uart when write to reg 0	trinklhar	6380d 09h	/
115	* empty log message *	trinklhar	6380d 23h	/
114	Uart 0.3	trinklhar	6382d 03h	/
113	Uart reset funkt	trinklhar	6382d 04h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6382d 05h	/