URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 134

Rev	Log message	Author	Age	Path
134	Added second test program for testing uart.	jlechner	6364d 15h	/
133	- Fixed bug with ST opcodes.	cwalter	6364d 17h	/
132	Added test program for testing uart.	jlechner	6364d 17h	/
131	Changed high active resets to low active ones.	jlechner	6364d 17h	/
130	Removed obsolete line	jlechner	6364d 18h	/
129	Sample assembler program for accessing uart	jlechner	6364d 18h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6364d 18h	/
127	Changed high active resets to low active ones.	jlechner	6364d 18h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6365d 00h	/
125	Fixed vhdl bugs	trinklhar	6365d 00h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6365d 00h	/
123	Removed UART again	trinklhar	6365d 01h	/
122	Removed UART again again	trinklhar	6365d 01h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6365d 01h	/
120	Added UART module to memory entity	trinklhar	6365d 01h	/
119	Uart wieder ausgebaut	trinklhar	6365d 20h	/
118	insert Uart address constant	trinklhar	6365d 20h	/
117	Uart im mem_stage	trinklhar	6365d 20h	/
116	writes to uart when write to reg 0	trinklhar	6367d 03h	/
115	* empty log message *	trinklhar	6367d 17h	/