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Rev Log message Author Age Path
36 - Testbench for RISE. cwalter 6450d 19h /
35 - Testbench for register file. cwalter 6450d 19h /
34 - Filex have been renamed to have tb prefix. cwalter 6450d 19h /
33 - Fixed process sensitivity list. cwalter 6450d 20h /
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.		 cwalter 6450d 20h /
31 - Added PC_RESET_VECTOR constant. cwalter 6450d 21h /
30 - Top level testbench for RISE. cwalter 6450d 21h /
29 - Initial version of IF stage with dummy instructions. cwalter 6450d 21h /
28 Added new register write enable signals. jlechner 6452d 15h /
27 Added new register write enable signals to component instantiation of register_file and wb_stage. jlechner 6452d 15h /
26 Applied VHDL indent. jlechner 6452d 15h /
25 netlist file for the memories
is needed for IMEM and DMEM		 ustadler 6453d 15h /
24 4k Data Instruction for Spartan 3 (Block RAM)
Added write enable to the entity		 ustadler 6453d 15h /
23 4k Data Memory for Spartan 3 (Block RAM)
Added write enable to the entity		 ustadler 6453d 15h /
22 testbench für die register file ustadler 6454d 04h /
21 überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt ustadler 6454d 16h /
20 - Fixed bug where SR fetch code locked wrong register. cwalter 6454d 17h /
19 Version 1.2 der register file ustadler 6455d 01h /
18 Update of pipeline schematics:
- Fixed errors
- Changed names of some signals so they are equal with VHDL code
- Added second register lock port		 jlechner 6455d 20h /
17 - Added new tests for pipeline stall signal.
- Added tests for register locking.
- Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM
OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.		 cwalter 6457d 18h /

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