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Rev	Log message	Author	Age	Path
59	- We don't want to lock registers the next cycle when we have stalled the previous stages. - Load opcodes also need to lock registers.	cwalter	6424d 05h	/
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6424d 06h	/
57	- applied indenting tool.	cwalter	6424d 06h	/
56	new sensitivity list	ustadler	6424d 06h	/
55	- clear_out must be initialized to '0'.	cwalter	6424d 08h	/
54	- Changed reset delay.	cwalter	6424d 08h	/
53	- Removed unused constant COND_NONE.	cwalter	6424d 08h	/
52	- stall_out must be initialized to '0'	cwalter	6424d 08h	/
51	- stall_out logic has moved to synchronous process.	cwalter	6424d 08h	/
50	- Added assembler example. - Added logic for stall_in. pc_next must not be updated on stall.	cwalter	6424d 08h	/
49	data can be ead asynchronous, data is written with the rising edge of the clk	ustadler	6424d 09h	/
48	- Added ModelSim files.	cwalter	6424d 11h	/
47	- Added GNU assembler patch.	cwalter	6424d 11h	/
46	- Added constant for RESET_VECTOR.	cwalter	6424d 13h	/
45	- Fixed latch for pc_next.	cwalter	6425d 04h	/
44	- Added another version of a register file which is a bit simplier.	cwalter	6425d 04h	/
43	Correct implementation of necessary unlocking signals that are conncted to register locking unit.	jlechner	6425d 05h	/
42	Modified input signals for register locking (testbench modifications): Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6425d 05h	/
41	Modified input signals for register locking: Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6425d 05h	/
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6425d 05h	/

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[/] - Rev 59

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